A selectable - bandwidth 3 . 5 mW , 0 . 03 mm 2 self - oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz

In this paper we present a dual-mode thirdorder continuous time Σ∆ modulator that combines noise-shaping and pulse-width-modulation (PWM). In our 0.18 μm CMOS prototype chip the clock frequency equals 1GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64dB and the dynamic range 71dB. In the 10 MHz mode the peak SNDR equals 58dB and the DR 65dB. This performance is achieved at an attractively low silicon area of 0.03mm and a power consumption of 3.5 mW.